A known method of making a lightly doped drain (LDD) gallium arsenide (GaAs) FET is illustrated in FIGS. 2(a)-2(g). In FIG. 2(a), a semi-insulating GaAs substrate 1 has an active layer 2, usually n-type, formed by a known technique, such as ion implantation, diffusion, or epitaxial growth As shown in FIG. 2(a), the active layer 2 appears to be disposed on the substrate 1 which is the situation when the active layer 2 is formed by epitaxial growth. Otherwise, the active layer 2 is an integral part of the substrate 1 and is disposed at a surface of the substrate In this application, the active layer 2 is referred to as part of the substrate with the understanding that it may be a distinct layer if epitaxially grown.
As illustrated in FIG. 2(b), a film 3 (not shown) of a gate metal, such as a refractory metal like tungsten (W) or a refractory metal silicide such as tungsten silicide (WSi.sub.x), is deposited on the surface of the substrate 1 by a known technique, such as sputtering or vapor deposition. A photoresist film 4 (not shown) is deposited on the gate metal film 3 and patterned by conventional photolithographic processing to produce a mask 4' where a gate electrode is to be present. Thereafter, the gate metal film 3 is etched by reactive ion etching (RIE), for example, using sulfur hexafluoride (SF.sub.6) or a mixture of carbon tetrafluoride (CF.sub.4) and oxygen (O.sub.2). After the etching, a gate electrode 3' is left on the surface of the substrate.
Subsequently, the photoresist mask 4' is removed and, as indicated in FIG. 2(c), dopant impurities producing the same conductivity type as the conductivity type of the active layer 2 are implanted in the substrate 1. The gate electrode 3' functions as an implantation mask so that the doped regions 5 and 5' on opposite sides of the gate electrode 3' are formed In accordance with conventional processing, an annealing step follows in which the temperature of the substrate is raised to activate the implanted dopant impurities and to repair crystalline damage inflicted by the ion implantation step. The doped regions 5 and 5' have a dopant concentration larger than that of the active layer 2.
A film 6, shown in FIG. 2(d), preferably an electrically insulating film, is deposited on the surface of the substrate 1 and on the gate electrode 3' by a conventional process, such as vapor deposition. The film is etched by RIE. As well known in the art, by controlling the degree of etching, the film 6 can be removed from the gate electrode 3' and from the surface of the substrate 1, leaving side wall films 6' disposed on the surface of the substrate, adjacent to and contacting opposite sides of the gate electrode 3', as shown in FIG. 2(e). Generally, those side wall films 6' have a width comparable to the thickness of the film 6.
The gate electrode 3' and the side wall films 6' are used as an implantation mask and, in another implantation step, dopant impurities producing the same conductivity type as the conductivity type of the active layer 2 are implanted in the substrate. This implantation step produces doped regions 7 and 7' on opposite sides of the gate electrode 3' and the side wall films 6'. The dopant impurity concentration within regions 7 and 7' is larger than the dopant concentration in the regions 5 and 5'. Portions of the doped regions 5 and 5' protected by the respective side wall films 6' are left in the substrate adjacent to and electrically connecting the doped regions 7 and 7' to the active layer 2, respectively. The resulting structure appears in FIG. 2(f).
Finally, as shown in FIG. 2(g), the FET is completed by the formation of source and drain electrodes 8a and 8b in contact with the most heavily doped regions 7 and 7', respectively. Regions 7 and 7' are the source and drain regions, respectively, of the FET.
The LDD FET structure of FIG. 2(g) is useful in suppressing the short channel effect in FETs that causes variations in the threshold voltage of the transistor as the gate length becomes smaller than a few microns. In addition, the short channel effect causes the threshold voltage of the FET to depend upon the voltage between the source and drain, affects the current cut-off capability of the FET, and increases the drain conductance. These effects still appear in LDD FETs having gate lengths below about 1 micron. In the FET shown in FIG. 2(g), current leakage through the semi-insulating GaAs substrate 1 between the doped regions 5, 5', 7, and 7' directly below the active layer 2 contribute to the undesirable characteristics collectively referred to as the short channel effect.
An additional known FET structure for suppressing the short channel effect by preventing the flow of leakage currents in a semi-insulating substrate is shown in cross-section in FIG. 3. That FET has the same structure as the transistor of FIG. 2(g) and additionally includes a doped region 9 within the substrate adjacent to and contacting each of the regions 7, 5, 5', and 7' as well as the active layer 2. The doped region 9 has a conductivity type opposite the conductivity type of the active layer 2 and the regions 7, 5, 5', and 7', thereby forming a large area pn junction. The pn junction prevents the flow of leakage current within the substrate and further suppresses the short channel effect for gate lengths as short as about 0.5 micron. However, the presence of the doped region 9 in the substrate forming a relatively large area pn junction significantly increases the capacitance between the source and gate electrodes 8a and 3'. The increase capacitance limits the upper end of the frequency range in which the FET can be used.
In order to overcome the reduction in frequency range brought about by the inclusion of the doped region 9 in the substrate 1, the FET structure shown in FIG. 4 has been proposed. In the structure of FIG. 4, the doped region 9 within the substrate 1 is present in the substrate only beneath and contacting the doped regions 5' and 7' and a part of the active layer 2 that is near the interface of the active layer 2 and the doped region 5'. Because the doped region 9 is not present beneath the source region 7, the capacitance between the source electrode 8a and the gate electrode 3' is not substantially increased by the presence of the doped region 9. However, the doped region 9 substantially prevents the flow of leakage current through the substrate because of the pn junction interposed between the doped regions on the source side of the FET and the doped regions on the drain side of the FET. Thus, the short channel effect is minimized without adversely affecting the high frequency performance of the FET.
A method of making the FET structure of FIG. 4 is illustrated in FIGS. 5(a)-5(g). Initially, as indicated in FIG. 5(a), an ion implantation mask 11' is formed. A photoresist film 11 (not shown) is deposited and patterned using conventional techniques to produce the photoresist ion implantation mask 11'. Afterwards, ion producing the second conductivity type region 9, usually a p-type region, are implanted in the substrate 1.
Mask 11, is removed and subsequently the steps illustrated in FIGS. 2(b)-2(g) are carried out as illustrated and described with respect to FIGS. 5(b)-5(g). Since those steps have already been described, it is not necessary to describe them again. However, in carrying out those steps, particularly the step illustrated in FIG. 2(b) as applied in FIG. 5(b), a mask alignment step is required In order to produce the structure of FIG. 4, the doped region 9 must extend slightly beneath the gate electrode 3'. In other words, the photoresist pattern 4' used to define the gate 3' must be aligned with the buried doped region 9 that has already been formed in the substrate. If the alignment is not precisely made, the structure of FIG. 6, rather than the structure of FIG. 4, may be produced In the structure of FIG. 6, the doped region 9 is present within the substrate 1 only adjacent part of the doped region, i.e., the drain region, 7'. Part of the doped regions 5' and 7' are still in direct contact with the semi-insulating substrate 1 and leakage currents can still flow through the substrate 1 between the source region 7 and drain region 7'. Alternatively, as shown in FIG. 7, if an alignment error opposite in direction from the error that produces the structure of FIG. 6 occurs, the doped region 9 may extend all the way to the source region 7, causing an undesired increase in source-to-gate capacitance.
As is apparent from the foregoing discussion, a method of producing the structure of FIG. 4 without the problem of aligning a gate electrode mask with the doped region 9 is desired in order to produce the structure of FIG. 4 reliably, minimizing the short channel effect in narrow gate FETs without adversely affecting the high frequency performance of those transistors.